1. Technical Field
The present invention relates to a comparator and an A-D converter. More particularly, the present invention relates to a comparator that outputs a comparison result obtained by comparing two signals and an A-D converter provided with the comparator.
2. Related Art
FIG. 1 shows a configuration of a comparator 300 provided with an A-D converter or the like. The comparator 300 includes a differential amplifier 310, a positive buffer 320, a negative buffer 330, and a latch core 340.
The differential amplifier 310 differentially amplifies a differential signal that represents a difference between two input voltages. The positive buffer 320 converts a positive output signal of the differential amplifier 310 into a logic level. The negative buffer 330 converts a negative output signal of the differential amplifier 310 into a logic level that is an inverse of the logic level of the positive buffer 320.
When in a latch condition, the latch core 340 holds the logic levels output from the positive buffer 320 and the negative buffer 330. Furthermore, when in a reset condition, the latch core 340 resets output ends of the positive buffer 320 and the negative buffer 330 to a prescribed logic level (for example, a positive logic level). Such a comparator 300 alternately transitions between the latch condition and the reset condition in sync with a sampling timing of the A-D converter.
During a time when such a comparator 300 transitions from the latch condition to the reset condition, kickback noise that returns to the differential amplifier 300 from the positive buffer 320 and the negative buffer 330 is generated. The following is a simple description of the reason that kickback noise is generated.
Because the positive buffer 320 and the negative buffer 330 include transistors at an input side, the positive buffer 320 and the negative buffer 330 have a parasitic capacitance that relies on a bias voltage. Because the positive buffer 320 and the negative buffer 330 output logic levels that are inverses of each other while in the latch condition, bias voltages that are different from each other are applied to the transistors at the input side. Accordingly, while in the latch condition, the positive buffer 320 and the negative buffer 330 have parasitic capacitances that are different from each other as seen from a side of the differential amplifier 310.
Because the positive buffer 320 and the negative buffer 330 are reset to have logic levels identical to each other while in the reset condition, bias voltages that are identical to each other are applied to the transistors at the input side. Accordingly, while in the reset condition, the positive buffer 320 and the negative buffer 330 have parasitic capacitances that are identical to each other as seen from a side of the differential amplifier 310. Because of this, fluctuation amounts of the parasitic capacitances of the positive buffer 320 and the negative buffer 330 are different during transition from the latch condition to the reset condition.
Here, where the parasitic capacitances of the transistors at the input side fluctuate, the positive buffer 320 and the negative buffer 330 emit charges to the differential amplifier 310 according to the fluctuation amounts of the parasitic capacitances. Because the fluctuation amounts of the parasitic capacitances are different during transition from the latch condition to the reset condition, the amounts of charge emitted by the positive buffer 320 and the negative buffer 330 are different. Accordingly, during transition from the latch condition to the reset condition, the positive buffer 320 and the negative buffer 330 supply differential mode noise (kickback noise) to the differential amplifier 310.
In the manner described above, the comparator 300 generates kickback noise. Accordingly, the comparator 300 must transition to the next latch condition after the kickback noise has sufficiently decreased since transitioning to the reset condition.
In a case where the sampling rate of the A-D converter is increased, the comparator 300 must operate at a high speed. However, where the comparator 300 operates at a high speed, the comparator 300 must transition to the next latch condition before the kickback noise is sufficiently reduced. In such a case, it is possible that a mistaken value caused by the effect of the kickback noise is acquired in the latch core 340 by the comparator 300.